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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6206BA/D
32K x 8 Bit Fast Static RAM
The MCM6206BA is a 262,144 bit static random access memory organized as 32,768 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic small-outline J-leaded packages. * * * * * Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary Fast Access Times: 12/15/20/25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems * Low Power Operation: 125 - 140 mA Maximum AC * Fully TTL Compatible -- Three State Output
MCM6206BA
J PACKAGE 300 MIL SOJ CASE 810B-03
PIN ASSIGNMENT
A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V CC W A A A A G A E DQ DQ DQ DQ DQ
BLOCK DIAGRAM
A A A A A A A A A ROW DECODER MEMORY MATRIX VCC VSS
A A A A A A DQ DQ DQ VSS
PIN NAMES
DQ DQ INPUT DATA CONTROL
. . .
COLUMN I/O COLUMN DECODER
A . . . . . . . . . . . . . . . . . . . . Address Input DQ . . . . . . . . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground A A
E W G
A CIRCUIT CONTROL
A
A
A
REV 1 10/9/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM6206BA 1
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA ICCA ICCA Output High-Z High-Z Dout High-Z Cycle - - Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 1.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature--Plastic Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns)
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Output High Voltage (IOH = - 4.0 mA) Output Low Voltage (IOL = 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min -- -- 2.4 -- Max 1 1 -- 0.4 Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) AC Standby Current (E = VIH, VCC = Max, f = fmax) CMOS Standby Current (VCC = Max, f = 0 MHz, E VCC - 0.2 V Vin VSS + 0.2 V, or VCC - 0.2 V) Symbol ICCA ISB1 ISB2 - 12 140 40 10 - 15 135 35 10 - 20 130 35 10 - 25 125 30 10 Unit mA mA mA
CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25C, Periodically sampled rather than 100% tested)
Characteristic Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin Cin CI/O Max 6 8 8 Unit pF pF pF
MCM6206BA 2
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted
READ CYCLE (See Note 1)
- 12 Symbol Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z Power Up Time Power Down Time tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL 12 -- -- -- 3 4 -- 0 -- 0 -- -- 12 12 6 -- -- 7 -- 6 -- 12 15 -- -- -- 3 4 -- 0 -- 0 -- -- 15 15 8 -- -- 8 -- 7 -- 15 20 -- -- -- 3 4 -- 0 -- 0 -- -- 20 20 10 -- -- 9 -- 8 -- 20 25 -- -- -- 3 4 -- 0 -- 0 -- -- 25 25 12 -- -- 10 -- 10 -- 25 ns ns ns ns ns ns ns ns ns ns ns 4,5,6 4,5,6 4,5,6 4,5,6 4,5,6 3 Min Max Min - 15 Max Min - 20 Max Min - 25 Max Unit Note s 2
NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL).
TIMING LIMITS
+5 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6206BA 3
READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 3)
tAVAV A (ADDRESS) tAVQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) HIGH Z DATA VALID HIGH Z tGHQZ tELQV tEHQZ
VCC SUPPLY CURRENT ISB
ICC
tELICCH
tEHICCL
MCM6206BA 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
- 12 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Write Pulse Width, G High Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 12 0 10 10 10 6 0 -- 2 0 Max -- -- -- -- -- -- -- 6 -- -- Min 15 0 12 12 10 7 0 -- 2 0 - 15 Max -- -- -- -- -- -- -- 7 -- -- Min 20 0 15 15 12 8 0 -- 2 0 - 20 Max -- -- -- -- -- -- -- 8 -- -- Min 25 0 20 20 15 10 0 -- 2 0 - 25 Max -- -- -- -- -- -- -- 10 -- -- Unit ns ns ns ns ns ns ns ns ns ns 5,6,7 5,6,7 4 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If G VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested.
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH Z HIGH Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6206BA 5
WRITE CYCLE 2 (E Controlled, See Note 1)
- 12 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 12 0 10 9 6 0 0 Max -- -- -- -- -- -- -- Min 15 0 12 10 7 0 0 - 15 Max -- -- -- -- -- -- -- Min 20 0 15 12 8 0 0 - 20 Max -- -- -- -- -- -- -- Min 25 0 20 15 10 0 0 - 25 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 3,4 Notes
NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
WRITE CYCLE 2 (E Controlled, See Note 1)
tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELEH tELWH tEHAX
Q (DATA OUT)
HIGH Z
ORDERING INFORMATION
(Order by Full Part Number) MCM 6206BA EJ
Motorola Memory Prefix Part Number
XX
X
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns) Package (J = 300 mil SOJ, E = Evolutionary Pinout)
Full Part Numbers -- MCM6206BAEJ12 MCM6206BAEJ15 MCM6206BAEJ20 MCM6206BAEJ25
MCM6206BAEJ12R MCM6206BAEJ15R MCM6206BAEJ20R MCM6206BAEJ25R
MCM6206BA 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
CASE 810B-03 300 MIL SOJ 28 LEAD
F DETAIL Z
28 15
N D 24 PL 0.18 (0.007)
M
1 14
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. S INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 -- 0.035 0.045 0.025 BSC 0 10 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 0 10 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77
TA
S
-AL G M
H BRK
0.18 (0.007) P -BM
T
B
S
E 0.10 (0.004) K DETAIL Z -TSEATING PLANE
C
R 0.25 (0.010)
S
S RAD TB
S
DIM A B C D E F G H K L M N P R S
MOTOROLA FAST SRAM
MCM6206BA 7
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MCM6206BA 8
*MCM6206BA/D*
MOTOROLA MCM6206BA/D FAST SRAM

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